TURANDOT

TURANDOT/Project

About TURANDOT

TURANDOT is building automotive-grade RISC-V processors, AI accelerators and the software around them, so that the next generation of European vehicles runs on open, European-made computing.

Overview

TURANDOT brings together European semiconductor manufacturers, technology providers, research organisations and automotive stakeholders to strengthen European capabilities in automotive computing. The project is developing a modular, interoperable RISC-V hardware and software ecosystem aligned with future software-defined, connected and automated vehicles.

Its planned work includes automotive-grade processors, AI/ML acceleration, reference architectures, verification and benchmarking tools, a common automotive IP repository and industrially relevant demonstrators. The project runs from 1 August 2026 to 31 July 2030.

Purpose

Objectives

  1. SO1

    High-Performance RISC‑V Processors

    Design and validate automotive-grade RISC‑V application processors and real-time processors for central, domain and zonal computing, supported by scalable interconnects.

  2. SO2

    Software Tools & Libraries

    Develop qualified hardware abstraction layers, software libraries and toolchains for automotive RISC‑V platforms, with support for real-time execution, standardised interfaces and software-defined vehicles.

  3. SO3

    AI/ML Accelerators & Other IP

    Develop automotive-focused AI and ML acceleration IP, spanning efficient inference, vector and DSP capabilities, and their integration with RISC‑V processors.

  4. SO4

    System Integration & Interfacing

    Enable modular integration of processors, accelerators, memory and interconnects through flexible system architectures and interoperable interfaces for automotive SoCs and emerging chiplet systems.

  5. SO5

    Benchmarking & Quality Assurance

    Develop portable benchmarking and quality assurance methods for automotive RISC‑V hardware and software, including performance, latency, determinism, power, functional safety and security evidence.

  6. SO6

    Demonstration & Building-Block Interoperability

    Validate project hardware, software and IP through automotive demonstrator platforms, industrial platform clusters and two application-processor-centric demonstration lines.

  7. SO7

    Common Repository for Automotive RISC‑V

    Establish a governed common automotive repository for reusable IP, interface specifications, tools, benchmarking evidence and platform metadata, with appropriate levels of access.

  8. SO8

    RISC‑V Positioning in Automotive

    Strengthen the position of RISC‑V in automotive computing through industry-aligned validation, OEM feedback, reference-platform compatibility and long-term adoption roadmaps.

  9. SO9

    Cooperation Model

    Develop a sustainable pre-competitive collaboration model connecting semiconductor manufacturers, IP providers, researchers and automotive stakeholders around common European RISC‑V building blocks.

Research pillars

Where the work happens

  1. 01

    Automotive RISC‑V Processors

    Application processors and deterministic real-time cores for future centralised, domain and zonal vehicle architectures.

  2. 02

    AI & ML Acceleration

    Automotive inference accelerators and processing IP for compute-intensive perception and intelligent vehicle functions.

  3. 03

    Reference Architecture

    A shared European automotive RISC‑V architecture with interoperable profiles, interfaces and reference-platform assumptions.

  4. 04

    Software & Toolchains

    Low-level stacks, software development and integration workflows aligned with automotive requirements.

  5. 05

    Safety, Security & Benchmarking

    Verification, benchmarking, quality assurance and evidence to support relevant automotive standards and certification workflows.

  6. 06

    Industrial Demonstrators

    Silicon demonstrators, automotive platform clusters and interoperable hardware/software validation environments.

Validation

7 demonstrators

Demonstrator 1

Automotive SoC & AI platform

RISC‑V test chips combining a high-performance real-time processor, a low-power security-focused processor and a generative-AI coprocessor based on in-memory computing.

Led by STMicroelectronics SRL
Demonstrator 2

Dependable AI-enabled RISC‑V MCU platform

A scalable RISC‑V microcontroller architecture for automotive edge computing, with a focus on functional safety, low-latency real-time performance and AI-based anomaly detection.

Led by Infineon Technologies AG
Demonstrator 3

Zonal RISC‑V microcontroller and microprocessor system

A multi-chip RISC‑V computing platform for zonal vehicle architectures, built for demanding real-time workloads that meet automotive safety requirements.

Led by NXP Semiconductors Germany GmbH
Demonstrator 4

Secure RISC‑V ASIC platform

A secure processor based on the open-source CVA6 RISC‑V core, validated first on FPGA and then as an ASIC, for applications with strict data integrity and confidentiality needs.

Led by Thales DIS France SAS
Demonstrator 5

ADAS AI application demonstrator

Pre-development of a RISC‑V application core with a vector extension, tuned for driver-assistance and infotainment workloads and validated through FPGA emulation.

Led by ZF Friedrichshafen AG
Demonstrator 6

Scalable RISC‑V sensor fusion platform

A configurable RISC‑V system-on-chip for intelligent edge nodes in the car, pre-processing sensor data close to the source to cut latency and relieve central computers.

Led by Robert Bosch GmbH
Demonstrator 7

RISC‑V HPC cluster for the E/E backbone

A high-performance cockpit computer at the heart of the vehicle electronics, handling displays, cameras and vehicle-level functions together with zonal modules.