Work Packages
TURANDOT’s work is organised into eight interconnected work packages, spanning requirements and architecture through hardware, software, integration, demonstration and exploitation.
WP1Requirements, Architecture & Automotive-Specific Features
Defines the functional, performance and architectural requirements for high-performance RISC-V automotive processors, ensuring compliance with safety, security and real-time constraints, and establishes the automotive reference architecture and its hardware, software and system-level interfaces.
WP2Supply Chain Infrastructure & EDA Tools
Ensures supply-chain and infrastructure readiness for automotive RISC-V chips: EDA tools and methodologies that capture and track functional-safety requirements from early design to physical implementation, based on configurable IP-XACT 2022 metamodels.
WP3High-Performance RISC-V Automotive Processors, Accelerators & other IPs
Designs, prototypes and validates RISC-V processing and acceleration IP blocks – real-time and application CPUs, AI accelerators and supporting system IPs – for real-time, safety-critical and AI-intensive automotive workloads, in line with ISO 26262.
WP4Software Stack for Automotive Applications
Develops, integrates and documents qualifiable safety and security SDKs for the TURANDOT processors and accelerators – runtime software, design tools and application porting – using virtual platforms to decouple software from hardware timelines.
WP5System Integration & Interoperability
Defines the TURANDOT automotive RISC-V reference architecture and designs and implements the TURANDOT chip and FPGA designs at system, RTL and physical level – the foundation for the demonstrators.
WP6Demonstrators, Benchmarking and Validation
Validates the TURANDOT hardware and software building blocks in demonstrators aligned with real automotive use cases, showing interoperability, safety, performance and scalability, and gathering feedback from OEMs and Tier-1s.
WP7Common Automotive Repository
Establishes the common repository of IP blocks, software tools and documentation, an automotive-grade RISC-V reference platform, clear rules for open, shareable and confidential IP, and standardised benchmarking and integration guidelines.
WP8Project Management, Dissemination, Communication & Exploitation
Coordinates the project and manages risks, quality, IPR and data; communicates and disseminates results; drives exploitation and standardisation, liaison with other initiatives and the European RISC-V collaborative business model.
Milestones
| ID | Milestone | Work packages | Month |
|---|---|---|---|
| MS1 | Kick-off meeting; launch of the website and LinkedIn channel | All | M1 |
| MS2 | Initial requirements collected and transferred | WP1 | M10 |
| MS3 | First Technology Advisory Board meeting | All | M12 |
| MS4 | TURANDOT automotive RISC-V architecture specification defined; repository architecture finalised | WP5, WP7 | M12 |
| MS5 | Real-time processor architecture specs complete; AI accelerators, SW and tool architecture defined | WP3, WP4 | M16 |
| MS6 | Delivery of initial IP-XACT 2022 metamodels | WP2 | M18 |
| MS7 | Intermediate requirements collected; runtime SW architecture for RISC-V defined | WP1, WP4 | M24 |
| MS8 | Application processors & accelerators RTL complete | WP3 | M24 |
| MS9 | Demonstrator platforms & evaluation procedure defined for all demonstrators | WP6 | M24 |
| MS10 | Benchmarking framework operational & data ingestion pipeline functional | WP7 | M24 |
| MS11 | FPGA prototypes validation complete | WP3 | M30 |
| MS12 | First silicon tape-out package (Demonstrators 1, 2 and 3) | WP3, WP5 | M30 |
| MS13 | Foundations of the “Airbus of RISC-V” and assessment of partners’ exploitation plans | WP8 | M30 |
| MS14 | SDV integration architecture defined | WP4 | M32 |
| MS15 | Final requirements collected; integration & validation framework operational | WP1, WP2 | M36 |
| MS16 | Second silicon tape-out package (Demonstrators 1, 4 and 6) | WP3, WP5 | M36 |
| MS17 | All demonstrators fully specified; first phase of physical and virtual demonstrators realised | WP6 | M36 |
| MS18 | Interface and integration guidelines for chiplet compatibility defined | WP5 | M36 |
| MS19 | Third silicon tape-out package (Demonstrators 2 and 5) | WP3, WP5 | M40 |
| MS20 | Architecture for automotive ADAS/infotainment workloads defined | WP4 | M40 |
| MS21 | Advanced-node silicon & safety validation | WP3 | M42 |
| MS22 | Use-case mapping finalised | WP7 | M42 |
| MS23 | Certification-ready design flow available | WP2 | M48 |
| MS24 | Complete IP portfolio integration package | WP3 | M48 |
| MS25 | Chips & demonstrator validations complete | WP6 | M48 |